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High Speed Counter/ Comparator Circuit that Provides a Large Number of Stages

IP.com Disclosure Number: IPCOM000107987D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 113K

Publishing Venue

IBM

Related People

Thompson, SP: AUTHOR

Abstract

Described is a high speed counter/comparator circuit that provides a large number of stages. The circuit is designed to operate at high clock rates, typically 45 MHz or higher, and is particularly applicable in graphics applications where pixel positioning is critical.

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High Speed Counter/ Comparator Circuit that Provides a Large Number of Stages

       Described is a high speed counter/comparator circuit that
provides a large number of stages.  The circuit is designed to
operate at high clock rates, typically 45 MHz or higher, and is
particularly applicable in graphics applications where pixel
positioning is critical.

      The design provides a large number of counter stages, typically
ten or more, whereby all but two of the stages operate at one-fourth
the operating frequency for non-critical applications.  The design
provides eleven bits of counter/compare functions that allow a
maximum pixel count of 2,047 pixels.  The counter/comparator is
designed to operate at high video frequencies.  This aspect makes the
use of prior-art counter and comparators difficult to implement and
the performance critical. In the prior art, look-ahead carry logic
was required for each stage and a large amount of logic and excess
load on flip-flops significantly slowed down the operation.

      In order to operate at high frequencies, the concept described
herein allows the first two stages of the counter to operate at full
speed and allows the remaining stages to operate at one fourth the
speed.  This allows the remaining sections to be implemented in logic
that does not need to be fast, enabling the remaining counter stages
to operate as a ripple counter.

      Fig. 1 shows the logic block diagram of the counters,
comparators and shift registers to form the various stages. Logic
blocks 1, 2, 9, 10, and 11 form the two-bit high speed counter
section.  A synchronous clear function is shown at the input of
blocks 1 and 10. The counter outputs +Q from logic blocks 2 and 11
are presented to bit comparator block 16.  Comparator logic block 16
is used to compare the counter value with the lowes...