Browse Prior Art Database

Method of Increasing Personal System Performance by Reducing Bus Cache Overhead

IP.com Disclosure Number: IPCOM000107999D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 171K

Publishing Venue

IBM

Related People

Aldereguia, AA: AUTHOR [+4]

Abstract

Described is a method of increasing the performance of a personal system by reducing the overhead associated with local bus cache invalidation cycles.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Increasing Personal System Performance by Reducing Bus Cache Overhead

       Described is a method of increasing the performance of a
personal system by reducing the overhead associated with local bus
cache invalidation cycles.

      Personal systems equipped with a dual-port memory controller
allows the processor and the system bus master to execute cycles
concurrently. This requires the processor local bus to be isolated
from the system bus.  The processor executes cycles from the local
bus cache while the system bus is accessing the system bus memory.
This prior-art aspect improved the system performance since the
processor and the bus master were running concurrently.

      However, part of the performance increase gained from the
isolation of the processor local bus and the system bus is lost.
This is because the memory controller is required to provide "snoop"
cycles in order to maintain cache coherency between the local bus
cache(s) and local memory. During the snoop cycles, the memory
address written to by the bus master is placed on the processor's
local bus.  The local bus cache(s) then invalidates that line (16
bytes) of cache, if present.

      The processor is held off its local bus for several clock
cycles during the invalidation, or snoop cycle.  This holding off
reduces system performance.  The local bus caches are designed to
update/fill or invalidate always a line (16 bytes) of cache.  In
other words, the smallest block of data the cache can update is a
16-byte block; therefore, the compare logic does not use address
lines A3-A0 when invalidating a line in the cache.

      The concept described herein concentrates on reducing the
processor bus snooping overhead so as to improve system performance.
For example, a typical snoop cycle might originate from a diskette or
hardfile.  The data transferred is usually loaded into system memory
in sequential blocks, either as 8, 16, or 32 bits.  The memory
controller would be required to perform an invalidation cycle for
every write cycle, but the snoop hit register will reduce the number
of snoop cycles performed by the memory controller.  In the case of
an 8-bit device transferring 16 bytes of data to a block of
sequential memory, the device will execute 16 write cycles.  The
snoop hit logic will only execute one invalidation cycle.  This is
because the processor will invalidate an entire cache line (16 bytes)
on every snoop and the next 15 sequential snoops will perform
redundant invalidation operations...