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Improved Isolation and Gate Level Formation Process

IP.com Disclosure Number: IPCOM000108014D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 131K

Publishing Venue

IBM

Related People

Ng, H: AUTHOR [+4]

Abstract

One of the critical challenges in producing ULSI MOSFET logic and memory chips is the successful formation of the isolation regions. In advanced chip technologies, the isolation regions are formed using the Shallow Trench Isolation (STI) process. This process is very complex and time-consuming, limiting its use in future manufacturing technologies.

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Improved Isolation and Gate Level Formation Process

       One of the critical challenges in producing ULSI MOSFET
logic and memory chips is the successful formation of the isolation
regions.  In advanced chip technologies, the isolation regions are
formed using the Shallow Trench Isolation (STI) process.  This
process is very complex and time-consuming, limiting its use in
future manufacturing technologies.

      The authors have developed an isolation oxide region-gate level
formation process that does not involve the STI process, and, as a
result, is much more manufacturable.  After the formation of the N or
P well and the capacitor, a layer of CVD oxide is deposited at a
thickness equal to the desired isolation region thickness. The
preferred thickness is 300 nm.  The isolation photo level is
patterned by photolithography.  The field implantation is performed
using the photoresist as the mask, adjusting the implantation energy
so that it penetrates the isolation oxide.  Using the isolation level
mask, the oxide is etched until approximately 50 nm - 100 nm of oxide
remains in the open area.  At this point, a low ion bombardment
energy (< 100 Volt DC Bias) etch process is used to remove the
remainder of the oxide, stopping on the silicon surface.  The
photoresist is removed and the wafers are cleaned, as shown in Fig.
1.  A sacrificial gate oxide approximately 25 nm is grown.  A layer
of boron nitride (BN) of thickness 40 nm is deposited using chemical
vapor deposition (CVD).  The BN is planarized back to the top of the
isolation oxide, as sho...