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Emitter Coupled/ Collector Coupled Logic Compatible with ECL

IP.com Disclosure Number: IPCOM000108016D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Shin, HJ: AUTHOR

Abstract

New high-speed low-power emitter-coupled/collector-coupled bipolar logic circuits are disclosed. In the new circuits, logic function is performed both at the emitter-follower stage and at the common-base stage through emitter coupling and collector coupling of single-emitter or multiple-emitter transistors. Being compatible with ECL, the new circuits can be mixed with standard ECL or NTL to improve performance, power dissipation, and logic-power vs. power-dissipation ratio.

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Emitter Coupled/ Collector Coupled Logic Compatible with ECL

       New high-speed low-power
emitter-coupled/collector-coupled bipolar logic circuits are
disclosed. In the new circuits, logic function is performed both at
the emitter-follower stage and at the common-base stage through
emitter coupling and collector coupling of single-emitter or
multiple-emitter transistors. Being compatible with ECL, the new
circuits can be mixed with standard ECL or NTL to improve
performance, power dissipation, and logic-power vs. power-dissipation
ratio.

      The first circuit disclosed in Fig. 1 consists of the
common-base collector-coupled logic stage (QI, RC, QC and VRX)
performing AND function of the inputs (I1, I2, ...) and the
emitter-follower output stage with ECL-compatible signal. The inputs
may be driven by the same kind of circuit as well as the standard ECL
gate. Note that the emitter follower of proceeding gate (with or
without emitter dotting) is emitter-coupled to the input (QEF, ...,
QEFN and QI). Thus, the current through RT is steered to QEF, QEFN or
QI depending on the levels at X and Y relative to the reference VRX
which is set at (VR + VBE).  If both X and Y are low, the
current flows through QI into RC bringing the output O low.
Otherwise, the current is not switched to I1. Because the levels at S
and T similarly affect the current into I2, combined logic of this
emitter-coupled/collector-coupled stage is OR-AND. The diode QC is
needed to clamp the low level of Z so that QI is not saturated when
more than one inputs conduct current (e.g., when X, Y, S, and T are
all low).

      Compared to the standard ECL, the new circuit provides AND
logic without consuming costly power of current-switch stage in ECL
or implements OR-AND with onl...