Browse Prior Art Database

Data Transfer Control Mechanism for a High Performance Parallel System Interface

IP.com Disclosure Number: IPCOM000108042D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 203K

Publishing Venue

IBM

Related People

Westcott, GR: AUTHOR

Abstract

Disclosed are the necessary hardware controls to interface a microprocessor to a high performance parallel system interface control chip, such as Applied MicroCircuits Corp's (AMCC's) High-Performance Parallel Interface (HiPPI) Source Module (1) or a similar high performance parallel system interface. This hardware is designed to minimize microprocessor dependency such that once the microprocessor initiates the HiPPI Source interface operation (2), the hardware controls the subsequent Source Packet data transfer with data transfer rates of up to 200 MB/second. This hardware and microprocessor combination could be used in adapters such as the one shown in Fig.

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Data Transfer Control Mechanism for a High Performance Parallel System Interface

       Disclosed are the necessary hardware controls to
interface a microprocessor to a high performance parallel system
interface control chip, such as Applied MicroCircuits Corp's (AMCC's)
High-Performance Parallel Interface (HiPPI) Source Module (1) or a
similar high performance parallel system interface.  This hardware is
designed to minimize microprocessor dependency such that once the
microprocessor initiates the HiPPI Source interface operation (2),
the hardware controls the subsequent Source Packet data transfer with
data transfer rates of up to 200 MB/second.  This hardware and
microprocessor combination could be used in adapters such as the one
shown in Fig. 1 that permits a supercomputer, such as an IBM 3090*,
to distribute major workloads to an accelerator consisting of a
plurality of high-speed workstations, such as the IBM RISC
System/6000*.  This clustered high-speed computation facility could
be attached to serial optical channel interfaces via an optical
cross-bar switch, such as the IBM 9032 ES Connection Director, which
is shown in Fig. 1.

      Figs. 2 and 3 illustrate the environment of the "Data Transfer
Control Mechanism" hardware.  These figures contain a High
Performance Parallel Interface (HPI) Chip 1 on the left, an Intel
80960 microprocessor (MP) interface 2 on the right and a collection
of registers, counters and miscellaneous hardware in the middle that
represent the disclosed hardware.  The preferred embodiment uses an
AMCC Source HiPPI Chip referred to as the HiPPI (HPI) chip, but the
same concept applies if that chip is replaced by any other HiPPI
interface control chip.  Figs. 2 and 3 show HiPPI Interface signals
(1) entering and exiting HPI Chip 1.  HPI Chip 1, also provides an
interface to the disclosed hardware that consists of data and control
signals.  The Source hardware's FIFO data input 3, shown in Fig. 2,
comes from the MP memory system.  Most of the HPI Chip's control
signals provide status about the HiPPI interface operation in
progress or require stimulus into the chip to keep the interface
operation proceeding to completion.  Normally, a microprocessor would
interface with HPI Chips 1 to receive this status information and
provide the required stimulus to keep the operation proceeding to
completion.  In this embodiment, the selected Intel 80960 MP 2 cannot
be tied up for long periods of time to control one portion of the
adapter, since there are many other tasks for it to perform.  The
disclosed hardware provides a means for MP 2 to initiate the Source
HiPPI interface operation and then the hardware assumes control of
the subsequent packet data transfer which may be up to 64 kilobytes.
The MP is only notified at the completion of the packet data transfer
or if there was an error in the process.

      The center of Figs. 2 and 3 contains the register portion of
the disclosed hardware.  The...