Browse Prior Art Database

Dedicated Pipeline Command Formatter

IP.com Disclosure Number: IPCOM000108045D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

DiNicola, PD: AUTHOR [+5]

Abstract

Disclosed is a device for efficiently providing input to a pipeline processor. This device gives an improvement over current means by off-loading the control processor of the task, thereby improving parallelism. The device supports the FPGP, 5080, and 3270 data streams. The new means also provides FIFO buffering between the pipeline processor and the control processor and interface module, thereby reducing idle conditions due to unequal processing speeds. An automatic means of serialization of command/data streams from VRAM to the pipeline machine and beyond is now possible, thus relieving the control processor from the task. In addition, the device provides automatic data conversion from display program format (e.g., fixed-point) to floating-point.

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This is the abbreviated version, containing approximately 52% of the total text.

Dedicated Pipeline Command Formatter

       Disclosed is a device for efficiently providing input to
a pipeline processor.  This device gives an improvement over current
means by off-loading the control processor of the task, thereby
improving parallelism.  The device supports the FPGP, 5080, and 3270
data streams.  The new means also provides FIFO buffering between the
pipeline processor and the control processor and interface module,
thereby reducing idle conditions due to unequal processing speeds.
An automatic means of serialization of command/data streams from VRAM
to the pipeline machine and beyond is now possible, thus relieving
the control processor from the task.  In addition, the device
provides automatic data conversion from display program format (e.g.,
fixed-point) to floating-point.

      The pipeline command formatter's position in a typical system
is shown in Fig. 1.  A detail of its internal state machine
architecture is given in Fig. 2.  Fig. 3 depicts the internal
architecture of the pipeline command formatter.

      The block diagram in Fig. 3 describes the data flow of the
Pipeline Control Module.  Note that the display program to pipeline
format data conversion hardware and the FIFO buffer reside in this
data flow.

      Pipeline Control Module is an independent block of hardware
dedicated to processing pipeline data sequences. The state machine is
as "generic" as possible.  Most of the transitions are programmable,
as well as many of the data path control signals.  The Pipeline
Control Module also contains a 16-bit control register which defines
the programmable transitions and control signals.

      The Pipeline Control Module data paths can be broken down into
two major areas: 3250/5080/CHAR data formatting, and output data
selection.  The data formatting logic takes an input word from the
FIFO data control block and converts it to a 32-bit IEEE
floating-point absolute coordinate.  The first step in this process
is to convert the input data from one of 9 formats to a 16-bit twos
complement integer.  The Pipeline Control Module control register
specifies which format the input data is in.

      The next step is to convert any input data that is relative
data to absolute data.  to do this, several registers (current
position X, current position Y, and current position Z) and a 16-bit
twos complement adder are provided.  If the input data is absolute
(specified by the Pipeline Control Module control register), the
Pipeline Control Module will add '0' to the data and update the
corr...