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Borderless Gate Contact: MO Local Interconnect Technology for Trench Gate MOSFETs

IP.com Disclosure Number: IPCOM000108049D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 180K

Publishing Venue

IBM

Related People

Ng, HY: AUTHOR [+4]

Abstract

The use of the trench gate structure for 0.2 um MOSFET memory and logic chips necessitates the use of new techniques for formation of the contact windows. In addition, borderless or self-aligned contact windows will be required to achieve the target circuit density.

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Borderless Gate Contact: MO Local Interconnect Technology for Trench Gate MOSFETs

       The use of the trench gate structure for 0.2 um MOSFET
memory and logic chips necessitates the use of new techniques for
formation of the contact windows.  In addition, borderless or
self-aligned contact windows will be required to achieve the target
circuit density.

      A contact window formation process for the trench gate
structure that is borderless to the subsequent local interconnect
level has been developed.  The process begins following the
definition of the trench gate structure and the formation of the
N+/P+ junctions (Figure 1).  A chlorine-based RIE process is used to
recess the gate material with respect to the silicon nitride and
silicon dioxide sidewall spacers and the isolation oxide.  Both
conducting regions should be etched at approximately the same etch
rate, which can be achieved with a chlorine-based RIE process (Figure
2).  Silicon dioxide is deposited by Chemical Vapor Deposition (CVD)
and subsequently planarized to the top of the sidewall spacers.  This
result is shown in Figure 3.  A layer of Boron Nitride (BN) is
deposited at a thickness of 20 nm.  A layer of oxide is deposited and
should be adjusted accordingly.  This oxide forms the dielectric
stencil for the local interconnect wiring shown in Figure 4.

      The local interconnect photo level is defined in photoresist by
photolithography (Figure 5).  The photoresist pattern is tran...