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Maximizing the Number of Zero Slack Paths that are Delay Tested

IP.com Disclosure Number: IPCOM000108052D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 174K

Publishing Venue

IBM

Related People

Driscoll, BP: AUTHOR [+3]

Abstract

While testing for AC defects of semiconductor devices, it is sometimes necessary to add additional delay to paths that experience collisions with other paths utilizing the same inputs and outputs. These collisions prohibit all paths from being tested without adding additional delay to their edge placement within a timed AC cycle. Disclosed is an algorithm that is used to maximize the number of paths that do not need slack added to their measured delay value.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Maximizing the Number of Zero Slack Paths that are Delay Tested

       While testing for AC defects of semiconductor devices, it
is sometimes necessary to add additional delay to paths that
experience collisions with other paths utilizing the same inputs and
outputs.  These collisions prohibit all paths from being tested
without adding additional delay to their edge placement within a
timed AC cycle.  Disclosed is an algorithm that is used to maximize
the number of paths that do not need slack added to their measured
delay value.

      In recent years the "tester-per-pin" architecture (also known
as per-pin) has become widespread in the test industry because of the
ability to control each tester channel independently of the others,
instead of sharing limited tester resources among many channels.
Utilization of this per-pin architecture has allowed the test
community to improve the quality of delay testing performed on both
logic and embedded memory devices.  This has been facilitated by the
tester's ability to measure path delays on all paths of each path
type instead of only the worst-case path of each path type.

      The Staggered Stim algorithm is used to provide the best
placement of all timed edges regardless of how many different paths
are being tested in a particular AC cycle. Each timing edge will be
positioned so as to maximize the number of AC tests actually
performed with no slack added (Fig. 1).

      In the first step of this algorithm, all paths in the timing
file are placed in descending order.  Once the longest path has been
determined, a value of zero can be placed in the corresponding table
entry for that input (launch point) and the path delay will be placed
in the output's (capture point) table entry.  This table, when
complete, will be used to position each input, clock and output for
every different type of AC cycle.

      The next step includes scanning the remaining paths for
occurrences of the same capture point.  The corresponding launch
point will be placed in the table at the capture point's timing value
minus the individual path delays for each launch point (launch =
capture - delay).  Once all paths containing the same capture point
have been processed, the table is scanned for another path containing
a new capture point.  If the launch point corresponding to this next
path has not already been set, then the decision to make an
assignment for this path should be delayed and the next path should
be chosen.  This delay will eliminate the need for readjustment at
the end of the algorithm.  When the new path is chosen, the capture
point should then be placed at the corresponding launch point plus
the delay value (capture = launch delay). The table is then scanned
to look for more occurrences of the same capture point and the
process is repeated.

      Closer examination of the timing data associated with each
unique design reveals that not all paths can be tested without addi...