Browse Prior Art Database

Macro Instruction Return Mechanism from ROS Execution

IP.com Disclosure Number: IPCOM000108054D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Henry, GG: AUTHOR [+3]

Abstract

Disclosed is a system employing a micro instruction processing node (micro sequencer) to emulate a complex instruction set computer (CISC). The micro sequencer is enhanced with a return instruction mechanism to speed up every complex instruction by one clock, thus increasing the throughput of the CISC processor.

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Macro Instruction Return Mechanism from ROS Execution

       Disclosed is a system employing a micro instruction
processing node (micro sequencer) to emulate a complex instruction
set computer (CISC).  The micro sequencer is enhanced with a return
instruction mechanism to speed up every complex instruction by one
clock, thus increasing the throughput of the CISC processor.

      In past implementations of micro sequencer emulation of complex
instructions, a return instruction by the micro sequencer is employed
to denote the micro sequencer is completing the complex instruction
and, therefore, free to trap to the next complex instruction. The
execution of this return instruction requires one clock by the micro
sequencer.  As seen in the sequence below, the micro sequencer
requires execution of a return before starting the next complex
instruction.

      OLD SEQUENCE                 NEW SEQUENCE
CLOCK   COMPLEX     MICRO              COMPLEX      MICRO
COUNT   INSTR       INSTR              INSTR        INSTR
 1       ADD A,B    LOAD R1,A          ADD A,B      LOAD R1,A
 2                  LOAD R2,B                       LOAD R2,B
 3                  ADD R1,R1,R2                    ADD R1,R1,R2
 4                  STORE R1,A                      STORE R1,...