Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Enhanced Verification of Sequence Detectors in State Machines

IP.com Disclosure Number: IPCOM000108058D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Lucas, GS: AUTHOR

Abstract

The nature of a sequence detector requires substantial added function if its functionality is to be ensured. This article describes how diagnostic microcode can be used to verify the functionality of a sequence detector which monitors interfaces managed by state machine sequencers. This methodology minimizes the amount of hardware required while taking advantage of microcode flexibility to verify that the detector is 100% functional.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced Verification of Sequence Detectors in State Machines

       The nature of a sequence detector requires substantial
added function if its functionality is to be ensured.  This article
describes how diagnostic microcode can be used to verify the
functionality of a sequence detector which monitors interfaces
managed by state machine sequencers. This methodology minimizes the
amount of hardware required while taking advantage of microcode
flexibility to verify that the detector is 100% functional.

      For designs that implement state machine logic to manage data
bus interfaces, it is key to have a sequence detector to ensure data
integrity as well as Error Detection and Fault Isolation (EDFI).
Movement of data as well as command and status information is
accomplished using a sequential protocol.  A set of "tag" signals is
used to identify unique states of the interface (i.e., selection,
parameter passing, commands, start and stop, etc.).  The sequences of
these tags define the interface scenarios. Only certain sequences are
valid.

      Maintaining parity across the tags is a requirement and
protects against single-bit tag failures as the tags leave or enter
the state machine.  A parity checker will catch this class of
failures.  More difficult to detect are logic failures within the
state machine that cause invalid states to be entered.  In this case
tag parity will be good but an illegal sequence occurs.  Protection
for this class of failures can be achieved by implementing an
"illegal" tag sequence detector.  This detector is straightforwa...