Browse Prior Art Database

Synchronous Clock Generator Circuit for Computer System Gate Arrays

IP.com Disclosure Number: IPCOM000108067D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Fallwell, BN: AUTHOR [+2]

Abstract

Described is a synchronous clock generator circuit that provides phase relation synchronization between two clock pulse circuits while maintaining a proper phase relationship. The circuit allows two high frequency clocks to generate synchronized pulses for computer gate array usage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Synchronous Clock Generator Circuit for Computer System Gate Arrays

       Described is a synchronous clock generator circuit that
provides phase relation synchronization between two clock pulse
circuits while maintaining a proper phase relationship.  The circuit
allows two high frequency clocks to generate synchronized pulses for
computer gate array usage.

      Computer processing systems often utilize one clock to function
with the processor, such as a 32 MHz clock, and a different clock to
function with the system bus, such as a 48 MHz clock.  The
asynchronous nature of the two clocks can cause a race condition to
occur that can lead to short precharge pulse widths and occasional
parity checks.

      Generally, in order to eliminate a race condition, the clock
inputs are required to be synchronized with the 48 MHz pulses and
delayed relative to the 32 MHz pulses.  While it is possible to use
32 MHz delayed in place of 48 MHz, or 48/2=24 MHz for 32 MHz, the
circuit would not have run at full speed.  This method can
potentially mask other gate array problems and/or code timing
dependencies.  Another method divides down from 96 MHz to obtain 48
MHz and 32 MHz pulses.  However, this requires additional high-speed
logic.

      Fig. 1 is a functional block diagram of the circuit of this
disclosure.  The concept described herein provides a synchronization
method which starts at 16 MHz oscillator 10, as shown in Fig. 1, and
generates both clock pulses...