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Protection Against Erroneous Correction by Faulty Circuit

IP.com Disclosure Number: IPCOM000108069D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Tran, TV: AUTHOR

Abstract

Described is an Error Correcting Code (ECC) method for correcting data if an error is detected in the data retrieved from memory. There are failure modes in ECC circuits that result in erroneous correction of one or more bits. These failures can lead to serious problems since the wrongly corrected data is relied upon by other hardware or microcode. This solution can be implemented in any system which employs ECC.

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Protection Against Erroneous Correction by Faulty Circuit

       Described is an Error Correcting Code (ECC) method for
correcting data if an error is detected in the data retrieved from
memory.  There are failure modes in ECC circuits that result in
erroneous correction of one or more bits.  These failures can lead to
serious problems since the wrongly corrected data is relied upon by
other hardware or microcode.  This solution can be implemented in any
system which employs ECC.

      Fig. 1 illustrates a typical ECC circuit.  The data bits and
associated ECC parity bits are fed to a Syndrome Generation circuit.
The generated syndrome is coupled to an Error Location circuit.  The
output signals from the Error Location circuit are coupled to a Data
Correction circuit which produces the corrected data.

      If errors exist in either the Error Location circuit or the
Data Correction circuit, the data will be wrongly modified.  Serious
problems result from incorrectly modifying control instructions,
data, or destination addresses of branch instructions and the like.
The damage may not be detected or recovery from such errors is very
difficult.

      The problem can be avoided using a parity predict or parity
correct method.  Fig. 2 shows the data bits and associated ECC parity
bits coupled to the Syndrome Generation circuit.  Parity is generated
across the data bits by the Parity Generation circuit.  The output
signals from the Syndrome Generation...