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Array Calculation for K-Simulation

IP.com Disclosure Number: IPCOM000108092D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Larson, BR: AUTHOR [+3]

Abstract

K-simulation can be used to identify non-controllable signals within a logic network. The basic algorithm is described in (1). (From that original design K-simulation was enhanced as described in (2) to support additional block primitives and their associated values (i.e., three-state devices and the high impedance value). The four logic values used by the algorithm are: X(non-controllable), 1 (controllable to 1 only), 0 (controllable to 0 only), and K (possibly controllable to both 1 and 0). How to build, for an arbitrary combinational function, the 4-valued truth table, which can be used to evaluate the function for K-simulation, is shown in (1), but the article does not give a method of deriving truth tables for complex sequential primitives (array). (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Array Calculation for K-Simulation

       K-simulation can be used to identify non-controllable
signals within a logic network.  The basic algorithm is described in
(1).  (From that original design K-simulation was enhanced as
described in (2) to support additional block primitives and their
associated values (i.e., three-state devices and the high impedance
value).  The four logic values used by the algorithm are:
X(non-controllable), 1 (controllable to 1 only), 0 (controllable to 0
only), and K (possibly controllable to both 1 and 0).  How to build,
for an arbitrary combinational function, the 4-valued truth table,
which can be used to evaluate the function for K-simulation, is shown
in (1), but the article does not give a method of deriving truth
tables for complex sequential primitives (array).

                            (Image Omitted)

      Given a sequential circuit described as an interconnection of
combinational logic primitives, it would be straightforward to
construct the K-simulator's 4-valued truth table for the sequential
circuit.  This would involve applying each possible input pattern to
the uninitialized (all X) circuit; carrying out the K-simulation, as
described in (1), for each pattern; and recording the results in the
truth table.

      The use of 4-valued truth tables for the K-simulator's
evaluation of sequential logic primitives would encounter two
problems.  The first, and largest, is that of size.  If a primitive
has as many as 16 inputs, its truth table would fill the entire
address space of a 32-bit addressable memory.  The second problem is
that the NAND-NOR level description of the primitive function is not
available. Therefore, one cannot use the algorithm of (1) to create
the truth table.

      This article describes a method of evaluating RAM and ROM
primitives in K-simulation.  The logic primitives are defined as
shown in the figure.  The figure shows single-port RAM and ROM
primitives.  Before explaining the algorithm, three concepts must be
developed:
Composite Signal Values

      The phrase "composite signal value" as used herein refers to
the result of combining a multiplicity of signal values into one.  In
accordance with the definitions of the five signal values X, 0, 1, K,
and H, if all the signal values to be combined are X, the composite
value is X.  If any signal value were 0, and none are 1, K or
H, then the composite is 0.  If any signal value were 1, and none are
0, K, or H, then the composite value is 1.  If any signal value were
H, and none are 0, 1, or K, then the composite signal is H.  If
any signal were K, or there was a mixture of 0 and 1, the composite
signal would be K.  Finally, if any of the above conditions were
true, AND the high impedance (H) signal also existed, the composite
signal includes the H value (i.e., 0H, 1H, KH, respectively).
Controllability of a Write Port

      A controllable write port is a wr...