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Circuit Scheme to Bias OCD Output Stage N-Well

IP.com Disclosure Number: IPCOM000108104D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Atallah, F: AUTHOR [+2]

Abstract

Tri-state OCD output stages, implemented in N-well CMOS technologies have the limitation of output voltages being driven no higher than one threshold above the OCD power supply (when in tri-state) by dotted sources. When a lower power supply potential is used on the output stage pull-up PFET source to minimize OCD power dissipation, concern arises regarding latch-up, if this tri-state OCD is dotted on to a network where other OCDs have a higher power supply. The following describes a simple circuit configuration comprised of only two PFETs, which provide the correct well bias to ensure no latch-up due to "overdriving" the output when in tri-state, while optimizing the overall switching performance of the OCD.

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Circuit Scheme to Bias OCD Output Stage N-Well

       Tri-state OCD output stages, implemented in N-well CMOS
technologies have the limitation of output voltages being driven no
higher than one threshold above the OCD power supply (when in
tri-state) by dotted sources.  When a lower power supply potential is
used on the output stage pull-up PFET source to minimize OCD power
dissipation, concern arises regarding latch-up, if this tri-state OCD
is dotted on to a network where other OCDs have a higher power
supply. The following describes a simple circuit configuration
comprised of only two PFETs, which provide the correct well bias to
ensure no latch-up due to "overdriving" the output when in tri-state,
while optimizing the overall switching performance of the OCD.

      Figs. 1A and 1B illustrate the output stage of a tri-state OCD
implemented in an N-well CMOS technology.  The source of device P1 is
connected to a 3.6-volt power supply. The drain of P1 is connected to
the OCD output which is also the drain of device N1.  The source of
N1 is connected to ground.  The gates of P1 and N1 are connected to
the circuitry comprising the pre-drive control logic.  This logic is
associated with a 5-volt supply.  The dual-power supply approach,
wherein the internal logic circuits are using the 5-volt supply and
the OCD output stages use the 3.6-volt supply, is being used to
minimize I/O power.  The N-well of the output PFET is connected to
the 3.6-volt supply.  When this configuration is used in a dotted
network, the maximum output voltage that the driver can attain when
driving a '1' is limited to the 3.6-volt supply. When tri-stated, the
network driving source cannot exceed 3.6 volts + 1 diode drop, lest
the output P-channel device P+ to N-well junction become forward
biased and induce latch up.  Since TTL logic is commonly used in
dotted networks, this output voltage limitation presents a problem.

      Clearly a simple solution would be to bias the P-channel device
N-well to 5-volts.  This would eliminate the forward bias condition
and allow other drivers to pull the output up to 5 volts.  The major
drawback of this simple approach is that the performance of output
PFET would suffer.  This performance degradation results due to the
increased source-to-bulk potential of 1.4 volts which will increase
(absolute magnitude) the PFET threshold voltage. Furthermore, since
the gate of the output PFET is driven from a circuit connected to the
5- volt supply, the time required to turn the PFET on...