Browse Prior Art Database

Processor with Logical Instruction Cache and Physical Data Cache

IP.com Disclosure Number: IPCOM000108109D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Kawase, K: AUTHOR [+3]

Abstract

Disclosed is a processor which has logical instruction cache and physical data cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

Processor with Logical Instruction Cache and Physical Data Cache

       Disclosed is a processor which has logical instruction
cache and physical data cache.

      A Harvard Architecture, which provides discrete instruction bus
and data bus, is very effective, because there is no bus contention
between instruction fetch and data manipulation.  Because of the
restrictions of the number of Input/Output pins, there used to be
employed an Internal Harvard Architecture for microprocessors.  The
Internal Harvard Architecture has discrete instruction and data bus
only inside of the chip; however, the external bus is merged to one.

      A TLB (Translation Lookaside Buffer) is provided for effective
address conversion between the logical address and physical address.

      Fig. 1(a) shows an Internal Harvard Architecture microprocessor
which has logical instruction cache and logical data cache.  This
implementation works effectively. However, when the logical address
space is changed by a process switch, all caches must be purged.
Moreover, it is difficult to maintain the cache consistency in the
multiple processor configuration.  These are disadvantages of the
logical cache.

      Fig. 1(b) shows an Internal Harvard Architecture microprocessor
which has physical instruction cache, physical data cache and one set
of TLB.  This implementation avoids the above problems; however, a
contention occurs at the TLB access.

      Fig. 1(c) shows an Interna...