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Low Power Semiconductor Circuits

IP.com Disclosure Number: IPCOM000108111D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Niijima, H: AUTHOR [+3]

Abstract

Disclosed are semiconductor circuits for low-power operation.

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This is the abbreviated version, containing approximately 100% of the total text.

Low Power Semiconductor Circuits

       Disclosed are semiconductor circuits for low-power
operation.

      Fig. 1 shows an inverter circuit.
1) The circuit consists of the six of FET, Input FETs (Q1, Q2)
Voltage limiters (Q3, Q4) and Current limiters (Q5, Q6). Current
limiters (Q5, Q6) are added on a demand basis.
2) Q1, Q3 and Q5 are N-channel FETs.
   Q2, Q4 and Q6 are P-channel FETs.
3) The circuit has two inputs, namely 'Pin' and 'Nin'.
   'Pin' receives a 'Pout' signal from the previous gate.
   'Nin' receives a 'Nout' signal from the previous gate.
4) The circuit has two outputs, namely 'Pout' and 'Nout'.
   'Pout' drives 'Pin' of the next gate.
   'Nout' drives 'Nin' of the next gate.
5) Voltage limiters (Q3, Q4) are inserted between input FETs (Q1,
Q2).
6) 'Pout' is fed-back to N-ch voltage-limiter (Q3).
7) 'Nout' is fed-back to P-ch voltage-limiter (Q4).
8) The voltage between Q3 and Q4 is fed to current limiters (Q5, Q6).
9) Input interface from standard CMOS circuits is archived by
connecting 'Pin' and 'Nin'.  Output interface to standard CMOS is
achieved by connecting 'Pout' and 'Nout'.

      NAND and NOR circuits are shown in Fig. 2.  The inverter
circuit above is used in these structures.