Browse Prior Art Database

Minimization of Parasitic Bipolar Effect in Short Channel Silicon MESFETs

IP.com Disclosure Number: IPCOM000108124D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Related People

Ebersman, B: AUTHOR [+2]

Abstract

An improved design of Si MESFET suitable for eliminating parasitic bipolar effects has been described. As channel length shrinks for more compact and denser integration, these MESFETs are plagued with short- channel effects (1). At high drain voltage VD electrostatic field generated in the depletion region near the drain of these MESFETs becomes high enough to create electron-hole pairs, leading to parasitic bipolar effects and substrate current. A positive feedback mechanism between electron-hole pair generation at the drain-end and a parasitic lateral bipolar transistor in parallel with the MESFETs causes an early breakdown and a limitation of the operating voltage. The onset of the bipolar action results in a "kink effect", and the flow of excess holes in the substrate creates substrate current.

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Minimization of Parasitic Bipolar Effect in Short Channel Silicon MESFETs

       An improved design of Si MESFET suitable for eliminating
parasitic bipolar effects has been described.  As channel length
shrinks for more compact and denser integration, these MESFETs are
plagued with short- channel effects (1). At high drain voltage VD
electrostatic field generated in the depletion region near the drain
of these MESFETs becomes high enough to create electron-hole pairs,
leading to parasitic bipolar effects and substrate current.  A
positive feedback mechanism between electron-hole pair generation at
the drain-end and a parasitic lateral bipolar transistor in parallel
with the MESFETs causes an early breakdown and a limitation of the
operating voltage.  The onset of the bipolar action results in a
"kink effect", and the flow of excess holes in the substrate creates
substrate current.

      For the processing of the proposed MESFETs a p-GaP layer with a
doping density of about 1017cm-3 and a thickness of about 5000 Ao,
should first be grown epitaxially on Si substrate.  Prior to this
growth the substrate should be prepared, for example, by RCA
cleaning, JF dip, and a thermal in situ cleaning at 900~C for about 5
minutes.  It would be followed by the growth of an n-Si layer for
active n-type channel.  The fabrication of the MESFET should then be
performed following the same method as for Si MESFET.  The schematic
structure of the MESFET would thus be as shown in Fig. 1.  As GaP is
lattice matched to Si, the GaP/Si interfaces would contain only a
minimal number of traps.

      If a high voltage VD is applied to the drain, the field in the
depletion layer at the drain becomes high enough to generate
electron-hole pairs.  Because of the influence of VD, while the
electrons of these pairs would tend to move to the drain contact, the
holes would be repelled downward toward p-GaP.  As doping level of
this p-GaP is quite low, and its width is small, it would be largely
depleted of free carriers, enhancing the flow of holes, and retarding
the flow of electrons into the undepleted region of GaP.

      The bandgap difference between the GaP and Si appear both as
conduction b...