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Detection and Identification of Asynchronous Logic in a Synchronous Environment

IP.com Disclosure Number: IPCOM000108128D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 123K

Publishing Venue

IBM

Related People

Rivero, JL: AUTHOR [+3]

Abstract

Described is a software facility designed to assist logic designers in the detection and identification of all problem boundaries between asynchronous and synchronous logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Detection and Identification of Asynchronous Logic in a Synchronous Environment

       Described is a software facility designed to assist logic
designers in the detection and identification of all problem
boundaries between asynchronous and synchronous logic.

      Typically, logic design involving asynchronous inputs in a
synchronous clock environment requires thousands of logic blocks.
The designer has the job of synchronizing all asynchronous inputs
before they are seen by the synchronous portion of the logic.  The
first step involves the location of where the synchronization is to
be performed.  In circuit logic with thousands of logic blocks, the
identification is tedious and prone to error.

      The concept described herein provides a process and an
algorithm that guarantees that all boundaries between asynchronous
and synchronous logic are identified.  With this identification, a
report is generated to indicate all the possible problem latches
involved in the design.

      Generally, asynchronous inputs to a logic network can arrive at
any time with respect to the network clock.  As a result, all of the
inputs must be analyzed to determine if a data-capture problem may
exist, since a data-capture problem can exist when the data-set-up or
data-hold times for the latch are not met.

      Fig. 1 shows a simplified logic network with synchronous and
asynchronous inputs utilizing two latches and a single clock.  Latch
1 is driven from an asynchronous input.  In this case, the designer
must investigate conditions for a possible asynchronous problem.
Latch 2 has a synchronous input; therefore, a data-capture problem
will not exist.

      Figs. 2a and 2b show the different cases that must be handled
in a complex logic network where gated clocks may exist.  For
example, where gated clocks exist, asynchronous problem areas can
occur when either the latch data port is asynchronous or when the
gate signal is asynchronous. Each of these potential problem areas
must be identified to the designer.

      So as to identify all problem areas, an algorithm is used based
on a propag...