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Browse Prior Art Database

Multiple Symbol ECC

IP.com Disclosure Number: IPCOM000108165D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 51K

Publishing Venue

IBM

Related People

Grice, D: AUTHOR [+4]

Abstract

For memory systems, composed of dynamic memory chips, that are required to supply high bandwidth, low latency, access to small blocks of data, it is important to keep as much of the address space non-busy as possible. Large dynamic memory systems also require an ECC scheme to protect the system from soft failures, and single chip failures. It is the balancing of the cost of these two requirements that is addressed by the Multiple Symbol ECC scheme presented here.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Multiple Symbol ECC

      For memory systems, composed of dynamic memory chips, that are
required to supply high bandwidth, low latency, access to small
blocks of data, it is important to keep as much of the address space
non-busy as possible.  Large dynamic memory systems also require an
ECC scheme to protect the system from soft failures, and single chip
failures.  It is the balancing of the cost of these two requirements
that is addressed by the Multiple Symbol ECC scheme presented here.

      The organization of the chip used to illustrate this principle
is 16 independent functional islands, each 32K by 9 bits.  It is
possible to place a request each cycle to an island that is not busy
with a previous request.  Each request takes 8 cycles to process so
it is possible to have 8 concurrent operations occurring in the chip.
However, if a request is made for a busy island, then the request
must wait until the island is free again, which increases the latency
for that request.

      The memory system under consideration was required to operate
on 128 bit entities.  Using either 9 bit symbol ECC, treating each
chip as a symbol, or 1 bit symbol ECC, spreading the chip over 9 ECC
words, results in a costly, underutilized memory system.  The 9 bit
symbol ECC scheme, for SEC/DED protection of a 64 bit double-word
(DW) requires 27 bits of protection.  This results in 11 chips/64 bit
DW. Spreading the chip data over 9 different DWs results in 9 DWs
being access...