Browse Prior Art Database

Low Level Output Device for Testing

IP.com Disclosure Number: IPCOM000108176D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Related People

Anderson, CJ: AUTHOR

Abstract

This disclosure describes how to use an I/O pin as an output for debugging an internal node of a chip and as an input for the standard operation of the chip when there is a shortage of I/O pins. When debugging a circuit design it is important to be able to monitor as many test points internal to the chip as possible. An input pad on a chip can double as a low-level output pad for a signal coming from an internal node. An output signal on the order of 10 mV can easily be monitored on an oscilloscope, but add minimal noise to an input with a voltage swing of greater than 300 mV. A circuit that generates a small signal on an input pad is shown in the figure. A small inverter is used to monitor the internal test node, because it will not significantly load or slow down the signal at the test node.

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Low Level Output Device for Testing

      This disclosure describes how to use an I/O pin as an output
for debugging an internal node of a chip and as an input for the
standard operation of the chip when there is a shortage of I/O pins.
When debugging a circuit design it is important to be able to monitor
as many test points internal to the chip as possible.  An input pad
on a chip can double as a low-level output pad for a signal coming
from an internal node.  An output signal on the order of 10 mV can
easily be monitored on an oscilloscope, but add minimal noise to an
input with a voltage swing of greater than 300 mV.  A circuit that
generates a small signal on an input pad is shown in the figure.  A
small inverter is used to monitor the internal test node, because it
will not significantly load or slow down the signal at the test node.
The second inverter is not required, but makes it easier on the
engineer testing if the output has the same polarity as the test
node.  The load transistor in series with resister is a voltage
divider so that the voltage across the pad is small and an off chip
driver is not required.  Other voltage dividing schemes can be used.
When a pad is being used as an output, the value of the input signal
is 0 since the voltage on the pad is 0-10 mV.  The input that is
being used to monitor a test node cannot be tested at a 1 value.
However, for most circuits, a testing scheme can be developed that
will allow for the use of most input pad...