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Reduction in Short Channel Effects in Self Aligned MESFETs

IP.com Disclosure Number: IPCOM000108185D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

de Souza, JP: AUTHOR [+3]

Abstract

The state-of-the-art self-aligned MESFET and MOSFET technology requires sub-micron gates for fast circuit operation and data transfer. However, at such gate geometries, encroachment of dopant during self-aligned source/drain implant due to lateral implant straggle causes increased sub-threshold leakage. This leads the threshhold voltage to drop to a negative value, the so-called short channel effect. This situation becomes worse if any dopant diffusion occurs during post-implant anneal. Sidewalls are typically used in both the Si MOSFET and GaAs MESFET technology to offset the lateral encroachment described above. The sidewall material is either SiO2 or Si3N4, both of which are typically deposited by PECVD.

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Reduction in Short Channel Effects in Self Aligned MESFETs

      The state-of-the-art self-aligned MESFET and MOSFET technology
requires sub-micron gates for fast circuit operation and data
transfer.  However, at such gate geometries, encroachment of dopant
during self-aligned source/drain implant due to lateral implant
straggle causes increased sub-threshold leakage.  This leads the
threshhold voltage to drop to a negative value, the so-called short
channel effect.  This situation becomes worse if any dopant diffusion
occurs during post-implant anneal.  Sidewalls are typically used in
both the Si MOSFET and GaAs MESFET technology to offset the lateral
encroachment described above.  The sidewall material is either SiO2
or Si3N4, both of which are typically deposited by PECVD.

      It has been demonstrated recently that the H present in the
plasma during PECVD of Si3N4 passivates dopant under the side wall
regions and this phenomenon is accentuated if the sidewalls are ion
bombarded prior to dopant activation anneal.

      The following process can circumvent the short channel effects.
In this process channel implant/capped annealing followed by the gate
deposition/patterning is performed in a conventional manner.
However, as will become apparent later, this process will require
thicker gates than used in a conventional process.  Furthermore,
after the gate patterning instead of performing a sidewall implant,
this process would require n+ source/drain im...