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Browse Prior Art Database

High Granularity Clock Generation

IP.com Disclosure Number: IPCOM000108197D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 138K

Publishing Venue

IBM

Related People

Allen, JJ: AUTHOR [+3]

Abstract

VLSI chips are becoming more complex with embedded processor and rams; therefore, they require more complex timings. The clock generation logic must provide many different clocks, as well as the ability to adjust these clocks to the timing requirements dictated by the chip logic. By matching the clocks to the design, the difficulty of timing analysis is greatly reduced. The High Granularity Clock Generation (HGCG) generates clocks that can be adjusted by small increments of time; in other words, the clocks have higher granularity than those of previous designs. In addition, the HGCG clocks exhibit minimal skew. The HGCG clocks are also unaffected by oscillator duty cycle or internal logic delays, unlike clocks from previous designs.

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High Granularity Clock Generation

       VLSI chips are becoming more complex with embedded
processor and rams; therefore, they require more complex timings.
The clock generation logic must provide many different clocks, as
well as the ability to adjust these clocks to the timing requirements
dictated by the chip logic.  By matching the clocks to the design,
the difficulty of timing analysis is greatly reduced.  The High
Granularity Clock Generation (HGCG) generates clocks that can be
adjusted by small increments of time; in other words, the clocks have
higher granularity than those of previous designs.  In addition, the
HGCG clocks exhibit minimal skew.  The HGCG clocks are also
unaffected by oscillator duty cycle or internal logic delays, unlike
clocks from previous designs.  The HGCG design used few external chip
components and took advantage of various device offerings from
"CMPHILO", a CMOS design technology.  Also, the HGCG produced no
design rules checking (DRC) violations.

      The HGCG is best described in stages as shown in Fig. 1.  The
first stage involved the generation of the B and C clocks for the
ring counter.  The second stage consisted of the actual clock
generation, including the necessary level-sensitive scan design
(LSSD) control.  The third stage was responsible for the clock
drivers and any necessary load balance.  The following sections will
describe each stage and the devices that were used.

      The HGCG uses a combination of a delay line and the
unsymmetrical effect of the CMOS inverting receiver to eliminate the
clock overlap hazard.  The inverting output of the CMOS receiver was
chosen because it produced 1.3 nsec of pulse shrinkage assuming
best-case delays.  With worst-case delays, this value increases to
2.8 nsec.  By selecting an 8.5-nsec delay line to be used with the
inverting receiver, the clock overlap was eliminated, and
approximately one nanosecond of margin was obtained.  The clocks
produced by this technique are shown in Fig. 2.  For hazard #2, the
combination of delay line and an inverting receiver produced only a
0.45-nsec overlap, which was easily controlled by adding clock
drivers between the L2 output of one latch and the L1 input of the
following latch (see Fig. 2).  These overlap calculations assumed a
maximum variation of 0.25 nsec for the delay and 0.78 nsec for...