Browse Prior Art Database

Programmable Address Extension Method for a Microprocessor

IP.com Disclosure Number: IPCOM000108198D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 144K

Publishing Venue

IBM

Related People

Comp, CM: AUTHOR [+4]

Abstract

This article describes a method to increase the addressing range of the Intel 8086, 80186, 8088, 80188, and 80286 ("real" address mode) microprocessors to greater than 1 Mbyte of storage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Address Extension Method for a Microprocessor

       This article describes a method to increase the
addressing range of the Intel 8086, 80186, 8088, 80188, and 80286
("real" address mode) microprocessors to greater than 1 Mbyte of
storage.

      The Intel 8086, 80186, 8088, 80188, and 80286 ("real" address
mode) can address 1 Mbyte of physical storage.  The 80286 provides a
"protect mode" of operation (which can access 16 Mbytes of storage);
however, this is not always a viable alternative because there is
typically a significant degradation in performance when running in
"protect mode," and it may take a large effort to convert "real mode"
Licensed Internal Code (LIC) to "Protect Mode" LIC.  A method to
address 2 Mbytes (without using protect mode) is to use the
microprocessor (MP) bus status control lines to select either data
storage or instruction storage.  It is also possible, with some
additional logic, to make the partitioning of storage selectable via
Licensed Internal Code (LIC).  The following list shows the three
possible configurations for storage using these methods.
o    One Mbyte total for instruction and data storage (i.e., any part
of the one Mbyte can be instruction or data storage).
o    One Mbyte for instruction storage only plus an additional one
(or more) Mbyte for data storage only. (The current design only
implemented two Mbytes total; however, data storage can be extended
beyond one Mbyte as described later in this article).
o    One Mbyte for instruction and data storage (i.e., any part of
the one Mbyte can be instruction or data storage) plus an additional
one Mbyte for data storage only.  (The current design only
implemented two Mbytes total; however, data storage can be extended
beyond one Mbyte as described later in this article).

      The bus status control lines indicate what type of bus
operation is to take place.  Fig. 1 defines these bus cycles as
implemented by Intel.

      By decoding the Memory Instruction Read, the Memory Data Read,
and the Memory Data Write bus cycle status, an additional DRAM
control line can be generated (in this implementation, an additional
CAS line).  An "MP type" select line could be used to select the type
of MP being used: 80286 or not 80286.  The new CAS line would be used
to select the high or low Mbyte of storage, as shown in Fig. 2. Fig.
2 does not show all the necessary control lines for the DRAM
controller but just the use of the two CAS lines (a DRAM controller
is not a new concept; however, the way the CAS lines are controlled
is new).

      Referring to Fig. 2, the Cycle Decode Logic (1) decodes the MP
bus cycle status lines and activates the I-fetch line (2) when a
memory i...