Browse Prior Art Database

Parallel Lookahead Macro Instruction Prefix Decode

IP.com Disclosure Number: IPCOM000108216D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 41K

Publishing Venue

IBM

Related People

Jeffries, K: AUTHOR [+2]

Abstract

Disclosed is a mechanism which decodes prefix instruction in parallel with the normal instruction in a complex instruction set computer (CISC) and translates these complex instructions into native RISC instructions (reduced instruction set computer instructions). The parallel decode allows for CPIs (cycles per instruction) below 1.0 to be achieved for the CISC-based instruction execution.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

Parallel Lookahead Macro Instruction Prefix Decode

       Disclosed is a mechanism which decodes prefix instruction
in parallel with the normal instruction in a complex instruction set
computer (CISC)  and translates these complex instructions into
native RISC instructions (reduced instruction set computer
instructions).  The parallel decode allows for CPIs (cycles per
instruction) below 1.0 to be achieved for the CISC-based instruction
execution.

      The Intel 80386 processor instruction set architecture (ISA)
has prefix type of instructions which modify the function of the next
sequential instruction.  The prefix is one byte long.  Thus, to
decode the prefix and the instruction preceding it in a single clock,
decode logic is placed in two spots: at the start of the current
instruction to be decoded and one byte next to the current
instruction. This requires two sets of decode logic.  Decoding single
byte instructions followed by any other instruction requires the same
dual decode logic as in the prefix decode logic as stated above.
Therefore, the decode logic and the instruction shifting logic can be
shared for both functions. Most of the single-byte CISC instructions
and prefix instructions are of high usage.  Therefore, pairing these
single-byte instruction types with any instruction is quite frequent.
One clock cycle is saved each time a pairing occurs, which, in turn,
leads to higher throughput when employing this type of
dual-instruction decoding as...