Browse Prior Art Database

Buried Gate Design for Reliable, High Performance FETs

IP.com Disclosure Number: IPCOM000108224D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 93K

Publishing Venue

IBM

Related People

Kasi, SR: AUTHOR [+2]

Abstract

Disclosed is a novel design for a FET device based Silicon-on-Insulator (SOI) technology, with its primary and only gate buried under the device channel. (Image Omitted)

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Buried Gate Design for Reliable, High Performance FETs

       Disclosed is a novel design for a FET device based
Silicon-on-Insulator (SOI) technology, with its primary and only
gate buried under the device channel.

                            (Image Omitted)

      Conventional FET fabrication places the gate stack at the
silicon surface early in the process sequence.  However, subsequent
processing steps, e.g., RIE, I/I, and wet-chemical treatments, can
impact the integrity of the gate-stack.  These concerns become more
significant as gate-dielectric thickness is reduced and FET
channel-length approaches the sub-0.5 m technology.  Additional
concerns as device dimensions shrink are word (WL)-to-bitline (BL)
capacitance, gate-to- diffusion M0 level shorts, junction
penetration, and metallization volume effects.

      A thick SiO2 layer is formed on a silicon substrate.  A deep
trench is defined in the layer using a nitride layer as the
etch-mask. Gate-stack metal contact (GC) is formed at the bottom of
the trench by collimated sputtering.  Doped polysilicon filling is
followed by RIE- etchback of the polysilicon using the disappearing
nitride layer as the mask.  Gate insulator (GI) fabrication under
either thermal or deposition conditions is followed by masking and
definition of openings for epitaxial Si overgrowth.  The oxide
surfaces are then cleaned of residue by partially wet-etching Te
oxide, followed by Epitaxial Lateral Overgrowth and Chemical
Mechanical Polish of Silicon over Insulator (1).  The diffusion areas
and the metal contact to drain (CD) are defined by a critical
mask-step, completing FET fabrication.

      In the present design, GC fabrication precedes that of GI;
therefore, refractory and RIE processing involved in GC fabrication
do not impact GI integrity.  Further, since the GI/Si interface...