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NAND Gate Circuit with Feedback

IP.com Disclosure Number: IPCOM000108232D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Michail, MS: AUTHOR

Abstract

A high-speed and low-power bipolar logic circuit is shown in the figure. The circuit shown uses four PNP transistors, one NPN transistor, and four resistors. A compensating capacitor may be used to speed up the circuit. These components are used to implement a 3-input NAND gate.

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NAND Gate Circuit with Feedback

       A high-speed and low-power bipolar logic circuit is shown
in the figure.  The circuit shown uses four PNP transistors, one NPN
transistor, and four resistors.  A compensating capacitor may be used
to speed up the circuit.  These components are used to implement a
3-input NAND gate.

      The circuit is broken into two sections.  The basic NAND
circuit, on the left, establishes the DC levels.  PNP input
transistors T1, T2, and T3 must be off, i.e., high input, to
establish the low level of this stage.  It is basically determined by
the power supply Ve.  The high level is established when one or more
of the input transistors T1, T2, or T3, is on, i.e., low input.  The
high-level voltage is basically determined by the power supply
voltage and the voltage drop across the resistor R2, i.e., (Ve +
Ic*R2), where Ic is the collector current of the conducting logic
transistors T1, T2, or T3.  The high level is maintained constant by
utilizing the NPN transistor T4, as a feedback, such that the voltage
across its base emitter junction is equal to (Ic * (R2+R3).  The
feedback means thus cause a constant current to be drawn by the input
transistor(s) while it is on.  The NPN transistor current is
relatively small (about 0.1 ma).  Therefore, the added power due to
feedback mechanism is small. Relatively fast vertical PNP transistors
will allow this circuit to operate at high speed.  A speed-up
capacitor C1 may be used in the...