Browse Prior Art Database

Cost Performance BiCMOS

IP.com Disclosure Number: IPCOM000108241D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Bergeron, DL: AUTHOR [+5]

Abstract

Process steps are described which permit adding npn transistors to conventional CMOS technologies without sacrificing either performance or density. The bipolar structures are added after completion of all CMOS structures by using relatively simple process steps. The npn emitter and base shapes are defined by a conventional n+ polysilicon (n+ poly) gate structure. Two different methods are described for interconnecting the npn emitter with other devices.

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Cost Performance BiCMOS

       Process steps are described which permit adding npn
transistors to conventional CMOS technologies without sacrificing
either performance or density. The bipolar structures are added after
completion of all CMOS structures by using relatively simple process
steps. The npn emitter and base shapes are defined by a conventional
n+ polysilicon (n+ poly) gate structure. Two different methods are
described for interconnecting the npn emitter with other devices.

      Conventional CMOS processing up through the boron
phosphosilicate glass (BPSG) layer is used to realize the structure
of Fig. 1.  Successive etch steps remove the thin layer of BPSG, the
salicide layer and the polysilicon layer so that both the base and
emitter may be implanted into the top of the exposed n-well as shown
in Fig. 2.  Next n+ polysilicon is deposited over the emitter window,
and a second planarizing layer of BPSG is reflowed over the entire
chip. Contact holes through the BPSG permit connections to the
desired diffusions and polysilicon electrodes using conventional CMOS
techniques. The resulting npn structure is shown in Fig. 3.

      A second alternative for connecting the emitter polysilicon to
other structures eliminates the need for an emitter contact hole
through the BPSG. If salicide etching is allowed to undercut one edge
of the emitter opening in Fig. 2, subsequent deposition of n+
polysilicon will contact the buried polysilicon line, as shown in
...