Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Corner Enhanced Field Effect Transistor

IP.com Disclosure Number: IPCOM000108246D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Machesney, BJ: AUTHOR [+2]

Abstract

Transistors are constructed having their conduction path comprised of very narrow mesas running from source to drain. Excellent sub-threshold slope, substrate sensitivity, and high conduction current per unit width is realized in these devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 73% of the total text.

Corner Enhanced Field Effect Transistor

       Transistors are constructed having their conduction path
comprised of very narrow mesas running from source to drain.
Excellent sub-threshold slope, substrate sensitivity, and high
conduction current per unit width is realized in these devices.

      Characteristics normally observed as parasitic conduction due
to unavoidable edges or corners of conventional trench bounded
devices are made to dominate over characteristics of plateau portions
of transistors by construction as described below and in Figs. 1
through 4.

      Referring to Fig. 1, conventional processing is used to form
silicon trench insulation (STI) regions 2 and pad oxide 4 on silicon
substrate 6.  Then, silicon nitride is deposited conformally and
etched anisotropically, e.g., by reactive ion etching (RIE) to form
100 nm wide nitride spacers 8 on each vertical edge.

      Referring to Fig. 2, polysilicon (PS) is deposited conformally
and etched by RIE to form (PS) spacers 10 on exposed sidewalls of
spacers 8.  By repeating the nitride and PS spacer definition steps,
alternating spacers of the two materials can be made to completely
fill the region between STI regions.  Then, PS spacers 10 are etched
away by RIE.  Then, oxide 4 is removed and RIE proceeds into
substrate 6 for about 100 nm.  Next, nitride spacers 8 and underlying
oxide 4 are removed. During this processing, STI regions 2 are
partially etched away.

      Referring to F...