Browse Prior Art Database

Programmed I/O Error Handling for the I/O Channel Controller

IP.com Disclosure Number: IPCOM000108267D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

Disclosed is an efficient way to handle all Programmed I/O (PIO) errors by the I/O Channel Controller (IOCC).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 84% of the total text.

Programmed I/O Error Handling for the I/O Channel Controller

       Disclosed is an efficient way to handle all Programmed
I/O (PIO) errors by the I/O Channel Controller (IOCC).

      PIO operations to the IOCC are directed to different address
spaces that can generate different error conditions. The IOCC logic
is partitioned into two sections: the Central Electronic Complex
(CEC) logic that operates at processor frequency and the remainder
that uses a 20 MHz clock.  The processor frequency may change for
different products.  The CEC section interfaces to the System I/O
(SIO) bus.  The PIOs are received by the IOCC over the SIO bus and
the CEC logic in the IOCC decodes an eight-bit Bus Unit ID (BUID)
field to determine if the IOCC is selected. If selected, the PIO
operation is transferred to the 20 MHz logic that further decodes the
different address spaces and checks if the PIO is valid.  Since the
CEC section does a minimal decode, the worst-case timing paths are
small, allowing the IOCC to run with faster (sorted) processors.

      During a PIO operation, the processor is locked by the IOCC and
all errors reported synchronously.  This enables the processor to
recover from errors with minimal hardware.

      The IOCC can handle multiple errors during a single PIO and
sequential errors during multiple PIOs.  This is accomplished in one
of two ways.  If a previous error is still logged in the IOCC and the
PIO requires a Translation Control Word (T...