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Store Packaging to Memory System with Double Word ECC in Conjunction with a Store Through Cache in a RISC System

IP.com Disclosure Number: IPCOM000108269D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 125K

Publishing Venue

IBM

Related People

Barrera, DD: AUTHOR [+3]

Abstract

The processor cache is designed as a store through cache. This means that all store requests, whether they hit or miss in the cache, are stored out to main memory. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Store Packaging to Memory System with Double Word ECC in Conjunction with a Store Through Cache in a RISC System

       The processor cache is designed as a store through cache.
This means that all store requests, whether they hit or miss in the
cache, are stored out to main memory.

                            (Image Omitted)

      The processor memory data bus is a double word bus. All
accesses to main memory are double word transfers and are double word
aligned.  Associated with the double word of data are eight Error
Checking and Correcting bits (ECC bits).  These ECC bits are used to
detect and correct errors in the data coming back from main memory.
The value of these ECC bits is directly related to the data being
transferred to/ from main memory.

      Because the processor has a store through cache, and because
the ECC bits are based on a double word of data, all store requests
that are cache misses and are less than a double word in length
require the processor to perform a read-modify-write sequence in
order to implement the store. Therefore, for a store request that
misses in the cache and is less than a double word in length, the
processor must:
1.  Read the double word from memory that contains the data to be
modified and check the ECC bits.
2.  Modify the double word read from memory with the data being
stored and regenerate new ECC bits for the new double word of data.
3.  Store the new double word of data and new ECC bits back out to
main memory.

      The read-modify-write sequence is a significant burden on the
memory bandwitdth because it requires so many cycles to complete the
request.  While the exact number of cycles to complete a read-modify-
write sequence depends on the processor speed and the speed of the
DRAMs being used in main...