Browse Prior Art Database

Simplified Table Lookaside Buffer Handling Mechanism for a Multiprocessor

IP.com Disclosure Number: IPCOM000108273D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Kawase, K: AUTHOR [+3]

Abstract

Disclosed is a Translation Lookaside Buffer (TLB)-handling mechanism for a multiprocessor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

Simplified Table Lookaside Buffer Handling Mechanism for a Multiprocessor

       Disclosed is a Translation Lookaside Buffer
(TLB)-handling mechanism for a multiprocessor.

      Translations between logical addresses and physical addresses
are done using the page table in the main memory. The TLB keeps some
re cently used translation pairs to reduce main memory access. During
a TLB hit, the processor need not refer to the page table in the main
memory. However, if a TLB miss occurs, the processor must refer to
the page table and update the TLB.

      Current processors deal with TLB misses by themselves. A TLB
miss causes a hardware trap, and a TLB maintenance handler is
initiated by software or hardware. Such TLB handling mechanisms are
usually very complex.

      The disclosed method provides a very effective TLB-handling
mechanism for the multiprocessor system shown in Fig. 1. One of the
processor elements works as a kernel processor, as shown in Fig. 2.
The kernel processor handles TLB misses caused by other processor
elements. Therefore, no processor element except the kernel processor
needs to provide a TLB-handling mechanism.

      Fig. 3 shows the details of the TLB mechanism of a processor
element. When a processor element detects a TLB miss, it locks its
execution pipeline and requests the kernel processor to supply a
correct address translation pair. When the kernel processor receives
the request, it walks and searches the page table and...