Browse Prior Art Database

Programmable Timings for Memory Controllers

IP.com Disclosure Number: IPCOM000108277D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 86K

Publishing Venue

IBM

Related People

Borkenhagen, J: AUTHOR [+8]

Abstract

This article describes a method of state machine design used in conjunction with memory control. A programmable memory controller is used to optimize memory timings by adding or removing states as needed. The technique is used to accommodate fast or slow components with one design. Additionally, one controller can support more than one system clock speed using this technique.

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Programmable Timings for Memory Controllers

       This article describes a method of state machine design
used in conjunction with memory control.  A programmable memory
controller is used to optimize memory timings by adding or removing
states as needed.  The technique is used to accommodate fast or slow
components with one design. Additionally, one controller can support
more than one system clock speed using this technique.

      This article describes a memory controller with programmable
amounts of delay.  Effectively, these adjustable controllers add
delay in the form of additional states between a memory enable and a
controller strobe for data.  Delay may also be required to ensure a
proper restore of the memory components.  DRAMs particularly have
many timing constraints that could require delay states within the
controller to ensure proper operation (i.e., address setup and hold
times, RE to CE delay, CE or OE time to data out at high impedance,
etc.).

      The programmable memory controller can be implemented in
several ways.  Card or controller identification inputs can be used
to determine what amount of delay is required when accessing the
memory.  Scan-only latches could also be used to program the proper
delay.  In this case, the system could not distinguish between a fast
and slow card.  A more preferable approach is to use a diagnostic
command to load a register with the desired delay.  This allows the
programmed value to be changed by the system (which could not be done
with identification inputs) without having to stop the system and
scan in a new value (which would have to be...