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Browse Prior Art Database

Sub-surface Local Interconnects

IP.com Disclosure Number: IPCOM000108317D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 144K

Publishing Venue

IBM

Related People

Harame, DL: AUTHOR [+5]

Abstract

Using conventional circuit design techniques, the level of integration obtainable in bipolar technologies is often limited by "wire-ability" -- that is, the number of gates which can be wired together using traditional back-end-of-line (BEOL) metallurgy. To minimize this problem, various local interconnect schemes have been proposed (often called M-0 processes). The aim of these processes is simply to provide local wiring as part of the front-end-of-line (with generally tighter groundrules than the BEOL), thus reducing the wiring burden on the BEOL and leading to greater wireability. In general, M-0 processes must make compromises between capacitance and resistance -- some provide low resistance/high capacitance wiring while others provide high resistance/low capacitance wiring.

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This is the abbreviated version, containing approximately 51% of the total text.

Sub-surface Local Interconnects

       Using conventional circuit design techniques, the level
of integration obtainable in bipolar technologies is often limited by
"wire-ability" -- that is, the number of gates which can be wired
together using traditional back-end-of-line (BEOL) metallurgy.  To
minimize this problem, various local interconnect schemes have been
proposed (often called M-0 processes).  The aim of these processes is
simply to provide local wiring as part of the front-end-of-line (with
generally tighter groundrules than the BEOL), thus reducing the
wiring burden on the BEOL and leading to greater wireability.  In
general, M-0 processes must make compromises between capacitance and
resistance -- some provide low resistance/high capacitance wiring
while others provide high resistance/low capacitance wiring.  It has
proved difficult to provide low resistance/low capacitance local
interconnects which are desired for high performance with a high
degree of wireability.  This article describes a process to form low
capacitance, low resistance local interconnects beneath the wafer
surface using modifications to standard trench processing techniques.

      Current bipolar/bi-CMOS processes generally utilize
oxide-lined, polycrystalline silicon-filled, deep trench isolation.
This initial deep trench processing is assumed, and the starting
point for the sub- surface interconnect process is this structure
following planarization.  A masked recess operation is then performed
on the trench-fill material, recessing the trench-fill
polycrystalline silicon where a wiring channel is desired.  A
relatively thin dielectric layer can then be deposited into the
wiring channel to electrically isolate the wiring channel from the
trench-fill poly-silicon and/or to prevent possible dopant
out-diffusion from the wiring material and/or to prevent reactions
between the wiring and trench-fill materials.  A top view showing the
recess mask and a cross-sectional view of this structure is shown in
Figure 1.  At this point, contacts to buried layers (such as a
subcollector in a bipolar process) can be fabricated by using another
masking level and removing the liner dielectric and the appropriate
oxide liner to expose the vertical surface of this buried layer.

      The recessed regions are then filled with a conductive film.
This film could be highly-doped poly-silicon, a metal silicide, or a
refractory metal.  The structures are then planarized using chemical-
mechanical polishing and/or reactive-ion etching (RIE), or some other
technique.

      Shallow isolation patterns are defined photolithographically
and shallow isolation trenches are etched into the wafer surface by
RIE or some other techniq...