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Multiprocessing System Memory Access Queue and Scheduling Apparatus

IP.com Disclosure Number: IPCOM000108323D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 91K

Publishing Venue

IBM

Related People

Hicks, D: AUTHOR [+4]

Abstract

This article provides a fast and efficient scheme to schedule processor memory requests in a multiprocessing system for access to a central memory directory and multiported interleaved shared memory. This scheme provides the capability to handle signal memory accesses quickly and to handle many simultaneous memory requests efficiently. Furthermore, it provides fairness to all processors, as well as timely response to high priority requests. This is accomplished by using a three-level scheduling scheme located in a CENTRAL MEMORY CONTROL UNIT.

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Multiprocessing System Memory Access Queue and Scheduling Apparatus

       This article provides a fast and efficient scheme to
schedule processor memory requests in a multiprocessing system for
access to a central memory directory and multiported interleaved
shared memory.  This scheme provides the capability to handle signal
memory accesses quickly and to handle many simultaneous memory
requests efficiently. Furthermore, it provides fairness to all
processors, as well as timely response to high priority requests.
This is accomplished by using a three-level scheduling scheme located
in a CENTRAL MEMORY CONTROL UNIT.

      The CENTRAL MEMORY CONTROL UNIT is shown in the figure. The
CENTRAL MEMORY CONTROL UNIT receives memory requests from multiple
processors via dedicated processor buses (PBUS).  It then schedules
them for a central directory check lookup for cache consistency, then
dispatches the requests to the appropriate memory bank.  The major
components of the CENTRAL MEMORY CONTROL UNIT are the three levels of
scheduling units:  the input queue control unit, the directory access
control unit and the memory queue control unit.

      The first level of scheduling is performed by the input queue
control unit.  The input queue control unit schedules incoming
requests from each of the processors.  There is a dedicated queue for
each PBUS.  If the queue is empty and the second level of scheduling
is not busy, then the request is scheduled to bypass the queue.
Otherwise, the request is scheduled on a first-in, first-out (FIFO)
policy per input queue.  However, in order to improve system
performance, some memory requests may require faste...