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Browse Prior Art Database

Imager Local Bus for Smart Camera SoC

IP.com Disclosure Number: IPCOM000108331D
Original Publication Date: 2005-Mar-22
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 82K

Publishing Venue

Motorola

Related People

Sek M. Chai: AUTHOR

Abstract

This paper is concerned with the design evolution of digital imaging SoC platforms from digital camera applications to smart camera applications. Smart cameras use computer vision algorithms that require higher frame rates beyond traditional image finishing in digital cameras. An Imager Local Bus is presented in this paper to support ever increasing smart camera requirements. A full SoC design, showing placement of peripherals and accelerator is described, with respective bandwidth ranges for the Imager Local Bus.

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Imager Local Bus for Smart Camera SoC

Sek M. Chai

ABSTRACT

This paper is concerned with the design evolution of digital imaging SoC platforms from digital camera applications to smart camera applications. Smart cameras use computer vision algorithms that require higher frame rates beyond traditional image finishing in digital cameras. An Imager Local Bus is presented in this paper to support ever increasing smart camera requirements. A full SoC design, showing placement of peripherals and accelerator is described, with respective bandwidth ranges for the Imager Local Bus. 

Keywords

Smart camera, system on chip, image sensor, bandwidth

1.     INTRODUCTION

Smart cameras use computer vision algorithms to “see and understand” the scene. The “see” portion of smart cameras requires machine vision algorithms to segment, classify, and identify objects; the “understand” portion includes complex learning algorithms to model and track objects. These intelligent imaging components can be the next leading marketable feature in consumer products, and can even surpass pixel resolution as the leading marketable feature. Readers are referred to [1] for more information about the digital imaging industry.

Because smart camera functions are likely to evolve from today’s standard digital cameras, it must leverage the chip architecture and development platform of current digital camera systems. Chip architectures for digital cameras are built to supply increasingly more processing power for traditional image finishing such as color interpolation, white balance, gamma correction, and compression because consumers demand larger pixel resolutions. Digital camera IC such as [2] has reported performance ranges up to 500 MIPs.

Similarly, smart cameras similarly need more processing power to address evolving computer vision algorithms. Early estimations of smart camera performance [3] indicate a need for more than twice the performance of the digital camera ICs. The higher performance requirements in smart cameras do not translate directly to a higher performance processor alone. The memory subsystem that supports the processors and hardware accelerators must sustain the increased memory bandwidth as well.

One of the largest consumers of memory bandwidth is the raw image data from external image sensors. In addition to the data transfers related to display of processed image (e.g. to an external LCD panel), the raw video data can easily saturate all available bus bandwidth. However, unlike display data to an LCD panel, raw video data is a continuous stream of data that must not be dropped. Display data is typically stored in a buffer and can be recalled at any moment, while video data is continuously being generated by the image sensor as time progresses.

In order to compensate for the real-time bandwidth requirements of the image sensor, designers have relied on wider bus (e.g. 64 bit bus) which cost silicon area and faster bus (e.g. increase clock rate) whi...