Browse Prior Art Database

On Line Performance Measurement

IP.com Disclosure Number: IPCOM000108335D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Caillet, JN: AUTHOR [+6]

Abstract

Disclosed is an On Line Performance Measurement mechanism for a data transmission system composed of a processor which controls some various adapters via a bus called 'LOCAL BUS' and a storage via the Local Bus, a Storage Adapter and a 'Data Store Bus'. It controls also via the 'Local Bus' a 'Service Adapter' in which is implemented the disclosed mechanism.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

On Line Performance Measurement

       Disclosed is an On Line Performance Measurement mechanism
for a data transmission system composed of a processor which controls
some various adapters via a bus called 'LOCAL BUS' and a storage via
the Local Bus, a Storage Adapter and a 'Data Store Bus'. It controls
also via the 'Local Bus' a 'Service Adapter' in which is implemented
the disclosed mechanism.

      The processor itself is controlled by a code running in the
data store. The mechanism allows measuring the activity of some
critical paths, at any time, in order to give traffic information
which can be used for statistics and to optimize the system
configuration. In this application, the "Local Bus' and the 'Data
Store Bus' activities are detected by two hardware indicators
respectively called 'LSB ACT' and 'DSB ACT' in Fig. 1. These two
indicators are activated on independent of the traffic running upon
the bus they are watching.

      On request the specific control code is called from the service
console and a measurement is performed as follows:
      1. The code loads a 'Programmable Timer Counter' (PTC) with the
measurement duration value.
      2. The code loads the bit 3 of a 'Programmable Mode Register'
(PMR) ON to select a Data Store Bus activity measurement or OFF to
select a local bus activity one.  At the same time it loads the PMR
bit 0 ON to start the measurement.
      3. From this time the PTC begins to decrement following its
control clock while the PAC begins to count with the same control
clock each time the selected Indicator, Local Bus or Data Store Bus,
is activated. The measurement stops as soon as the PTC value reaches
0. The hardware logic resets the PMR bit 0 off.
      4. The code reads the result in the PAC register.

      The ratio PAC/PTC value gives the traffic rate of the selected
path, Local or Data Store Bus.

      This measurement gives at any time the system working status
and allows eventually to adjust the system configuration to optimize
it depending on some adapters working session time frame. It has a
minor impact on the Functional mode as the code is called and...