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In Vitro Translation Look Aside Buffer Test

IP.com Disclosure Number: IPCOM000108344D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 120K

Publishing Venue

IBM

Related People

Cheng, JC: AUTHOR [+3]

Abstract

Disclosed is a general program flow description that can help an assembly language programmer to test the translation look-aside buffer hardware of a processor whose architecture supports virtual memory implementation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

In Vitro Translation Look Aside Buffer Test

       Disclosed is a general program flow description that can
help an assembly language programmer to test the translation
look-aside buffer hardware of a processor whose architecture supports
virtual memory implementation.

      Most processor architectures, RISC or CISC, support the mapping
of very large virtual memory into a relatively small physical memory.
Their translation hardware normally uses Translation Look-aside
Buffer (TLB) to save the most recently used virtual addresses to
speed up the translating process.  If a valid TLB entry contains the
desired virtual address (i.e., a TLB hit), then the real physical
address will be found during the TLB lookup.  Normal translation
carried out by the hardware only occurs after the TLB lookup fails.
When the hardware address translation is accomplished, the hardware
will then update the TLB accordingly.  This entire process is
transparent to programs running in virtual memory.

      In general, TLB is not directly accessible from assembly
language instructions.  In order to test the functioning of TLB
hardware logic (i.e., entry selection, virtual address comparison,
and TLB Hit/Miss signal generation), the test will rely upon the fact
that an address translation failure results in a page fault
exception.  This technique is applicable to many computers which have
TLB implementation.

      Since TLB test is intended to be a part of the machine's IPL
process, the TLB test code will reside in ROM. However, the test will
require some use of RAM.  Therefore, enough good system memory should
be available.  All TLB entries must be invalidated and the processor
must be in privileged state before starting the TLB test.  These
conditions are normally met by the processor chip's initialization
during reset state.

      The program flow description of the test is given below:
      a. Establish a page-fault exception handler.  The handler will
set a dedicated general-purpose register to a 1 when it takes
control.  It must make sure that the instruction causing the fault
will not be restarted, and the faulting page will be fixed up so as
not to be faulted again.
      b. Move required test code from ROM to RAM.  The RAM code will
then be called from the ROM code.  This reduces the size of the
tables used by the translation hardware since ROM addresses normally
reside at the top of the memory map.  This also makes the table set
up easier.
      c. Set up tables required by the translation hardware, such as
Page Frame Table, Hash Table, etc.  These tables should be built such
that virtual addresses will be translated to the same real addresses.
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