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Browse Prior Art Database

Method of Front Side Substrate Contact

IP.com Disclosure Number: IPCOM000108347D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Hwang, B: AUTHOR [+3]

Abstract

This article describes a process to achieve a low resistance front side contact to a P-/P+ substrate.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Method of Front Side Substrate Contact

       This article describes a process to achieve a low
resistance front side contact to a P-/P+ substrate.

      This novel process consists of a series of ion implant,
oxidation anneal and selective epi deposition steps which results in
a lower resistance path to the P+ substrate than previously used
techniques.  The process is described below referencing Figs. 1-5.
      1.  A P-/P+ substrate (about 5 mm P- epi) with 200 Ao screen
oxide and 500 Ao silicon nitride layers.
      2.  Photoresist to protect desired substrate contact region;
      3.  Remove 500 Ao silicon nitride by using RIE;
      4.  Arsenic ion implantation, 50 KeV, 1E16/cm2 to form regular
Nsubcollector.
      5.  Strip photoresist.
      6.  Subcollector drive-in anneal and re-oxidation of Z 5000 Ao
(Fig. 1).
      7.  Remove 500 Ao silicon nitride and 200 Ao oxide from
substrate contact region.
      8.  Recess silicon of Z 1 mm.
      9.   Boron ion implantation, 80 KeV, 1E15/cm2 .
      10.  Boron drive-in anneal (Fig. 2).
      11.  Selective epi silicon deposition of Z 1 mm (silicon film
is boron-doped to 1E18/cm3).
      12.  Remove 5000 Ao oxide and deposition of regular N- epi.
      13.  Link-up boron ion implantation, 100 KeV, 1E15/cm2 and R1
resistor boron ion implantation, 30 KeV, 3.3E14/cm2 (Fig. 3).

      SIMS profile of described process results greater l...