Browse Prior Art Database

Common Planar Upgradable Memory Configuration Scheme

IP.com Disclosure Number: IPCOM000108350D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Howell, LC: AUTHOR [+2]

Abstract

This article provides a scheme to provide a low-cost memory subsystem with a minimum set of memory cards and, by simply plugging additional memory cards into the same planar, a high performance system with the memory width doubled is provided. This system provides the opportunity for a customer to buy a workstation with a minimal set of memory cards. Then, later, with no changes to the planar, hardware, or software, the customer can add additional memory cards and get not only an increase in the memory size but also a data bus twice as wide and, in turn, a system with twice the memory performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Common Planar Upgradable Memory Configuration Scheme

       This article provides a scheme to provide a low-cost
memory subsystem with a minimum set of memory cards and, by simply
plugging additional memory cards into the same planar, a high
performance system with the memory width doubled is provided. This
system provides the opportunity for a customer to buy a workstation
with a minimal set of memory cards.  Then, later, with no changes to
the planar, hardware, or software, the customer can add additional
memory cards and get not only an increase in the memory size but also
a data bus twice as wide and, in turn, a system with twice the memory
performance.

      The figure shows the partition of the processor chips and
memory.  In this partition an On Card Sequencer (OCS) interfaces with
Common Onchip Processor (COP) logic in each processor chip over a COP
bus. The OCS/COP initializes the chips and performs various test
functions at power-up. During functional operations data is moved
into and out of memory over either a 4-word or an 8-word memory data
bus. The Fixed Point Unit (FXU) and the Storage Control Unit (SCU)
control the movement of data in and out of the Dcache chips (DCU).
The OCS monitors a signal on the planar from the memory card slots
and during IPL it initializes a mode latch in the FXU, SCU, and DCU,
indicating the width of memory bus. This mode latch is used by the
processor chips to determine the number of cycles data will be moved
on the mem...