Browse Prior Art Database

LSSD-Compatible Edge Sensitive Circuits

IP.com Disclosure Number: IPCOM000108358D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 23K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

When designing in an LSSD (level-sensitive scan design) environment, it is common to find functions which lend themselves to an edge-sensitive design. An example of this is logic interfacing to an asynchronous I/O bus which has specifications from asynchronous edges which are very timing critical. In the IBM RISC System/6000* I/O Channel Controller (IOCC) design, a circuit was implemented which allows edge-sensitive designs to be used in a LSSD CMOS custom chip design. This allows the design to be less timing critical, increases performance while minimizing the logic complexity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

LSSD-Compatible Edge Sensitive Circuits

       When designing in an LSSD (level-sensitive scan design)
environment, it is common to find functions which lend themselves to
an edge-sensitive design.  An example of this is logic interfacing to
an asynchronous I/O bus which has specifications from asynchronous
edges which are very timing critical.  In the IBM RISC System/6000*
I/O Channel Controller (IOCC) design, a circuit was implemented which
allows edge-sensitive designs to be used in a LSSD CMOS custom chip
design.  This allows the design to be less timing critical, increases
performance while minimizing the logic complexity.

      Advantages are:
      -  allows an LSSD design to generate timing from asynchronous
edges,
      -  minimizes complexity required to implement function, and
      -  reduces timing critical designs.
*  Trademark of IBM Corp.