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Processor Idle for the Massively Distributed Simulation Engine

IP.com Disclosure Number: IPCOM000108371D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 151K

Publishing Venue

IBM

Related People

Beece, DK: AUTHOR [+2]

Abstract

A technique is described whereby a processor idle feature for the massively distributed simulation engine (MDSE) alleviates the need for non-operation (NOP) instructions and multiple simulation cycles. The result is an increase in effective capacity and performance. The encoding used as part of this idle function allows a dynamic check on all logical data sent throughout the machine.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 47% of the total text.

Processor Idle for the Massively Distributed Simulation Engine

       A technique is described whereby a processor idle feature
for the massively distributed simulation engine (MDSE) alleviates the
need for non-operation (NOP) instructions and multiple simulation
cycles.  The result is an increase in effective capacity and
performance.  The encoding used as part of this idle function allows
a dynamic check on all logical data sent throughout the machine.

      In prior art, a new special-purpose simulator, the MDSE, was
described.  In the concept described herein, a processor idle feature
for the MDSE is implemented which increases the effective performance
and the capacity of the system.  The idle feature combines the
encoding of data sent between the different parts of the MDSE with
counters so as to control the state of each processing element.  In
addition, the encoding that supports the processor idle function
provides a check on the data being sent between different parts of
the machine.  This provides a mechanism to detect and report on
dynamically occurring hardware errors.

      Since the MDSE does two-valued logic simulations, data sent
between processing elements (logic chips) must encode the logical
values "0" and "1".  The processor idle uses a third value to
represent the idle state of the sender, i.e., when the program
counter on a chip is not being advanced to the next instruction.
This idle value, which is output by the chip instead of a "1" or "0",
is generated after the results of a non-idling chip, i.e., the local
and external chip outputs have been sent off-chip.  The number of
idle states for each processor is determined at model compile time
and is stored in the chip's instruction memory as part of the
description for each gate.  This count indicates the number of cycles
the chip waits after a gate has been evaluated and before it advances
its program counter.  The count can be zero, in which case the chip
does not idle.

      The idle value is used to control the input to each logic chip.
When a logic chip is reading data from its inputs, it checks to see
whether it is a "0", "1" or idle. If the data is a logical value,
then it is stored into the appropriate location in data memory and
the location counter is incremented to the next write address.  If
the data's value is idle, then it is not stored and the location is
not incremented, therefore, the contents of the chip's data memory
are not changed.

      The three values "0", "1" and idle are encoded by using a
triple with exactly one bit set.  "1" is encoded by the triple 001;
"0" with the triple 010; while idle is the triple 100.  Since no
other triples are used, this encoding will detect any single bit
error, since such errors will cause the number of "1"s in the triple
to be different from one.  Triples are sent on each data path on the
MDSE (wire, chip output) by splitting each 75 nsec. instruction cycle
into three 25-nsec...