Browse Prior Art Database

Flexible Assembler/ Disassembler of an Aggregated Communication Link

IP.com Disclosure Number: IPCOM000108372D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 6 page(s) / 252K

Publishing Venue

IBM

Related People

Bond, AL: AUTHOR [+3]

Abstract

In a communication system that is required to accommodate a diverse set of data formats, being independent of data sequences and bit structures is very desirable. This dynamic requirement can be satisfied by configurable operating parameters, sequential table pointers, and hardware algorithms controlled by state machines. This concept utilizes a bit to bit inspection instead of octets or frame intervals to satisfy a wide variety of communication information formats of a T1/CEPT with a single solution.

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Flexible Assembler/ Disassembler of an Aggregated Communication Link

       In a communication system that is required to accommodate
a diverse set of data formats, being independent of data sequences
and bit structures is very desirable.  This dynamic requirement can
be satisfied by configurable operating parameters, sequential table
pointers, and hardware algorithms controlled by state machines.  This
concept utilizes a bit to bit inspection instead of octets or frame
intervals to satisfy a wide variety of communication information
formats of a T1/CEPT with a single solution.

      The advantages of this type of architecture are:
      .    Frame length and multi-frame length independence
      .    Bit or channel length variability within a frame structure
allowing different channel bandwidths to coexist.
       .   Independent data link control (DLC) detection and
formatting on a bit, channel, or frame basis.
       .   System flexibility to reconfigure a single physical
structure to accommodate multiple communication attachments, thereby
allowing the repeated utilization of one design for many different
communication applications.

      The interpretation of each bit in a serial bit stream as an
independent entity creates maximum flexibility to assemble or
disassemble any aggregated bit stream.  In communication
applications, a framing synchronization must first be established.
Once this has been achieved, based upon a specific communication
carrier framing structure, the concept is applied.  This bit
detection mechanism can be expanded to include logical framing and
algorithms for detection and establishment of other framing
structures. Typically, these structures are multiples of the standard
frame, such as those described in literature as Superframe, as
illustrated in Fig. 2, or Extended Super Frame.

      The overall bit/data flow to perform this assemble/disassemble
procedure are listed in the steps that follow (see Fig. 1).
      1.  Bit Synchronization established (frame alignment)
      2.  Bit Times Translated into Bit Identifiers (frame bits
numbered)
      3.  Bit Identifiers select a Bit Control Word Pointer (indirect
address for location of the control field)
      4.  Bit Control Word Pointer selects the Bit Control Words
(BCWs)
      5.  Bit Control Words are combined with current bit/data
      6.  Stored bits, control parameters, and operating status are
manipulated through the BCW registers and the Algorithm Arithmetic
Unit (AAU).
      7.  Modified control and operating status plus current bit/data
stream are placed back in the selected BCW.
      8.  Concatenated bits/data for this particular TDM channel slot
and the associated control flags are placed in main storage (the
queueing buffers for all bit channels).
      9.  Once a complete message or packet has accumulated in main
storage, a status flag is set...