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VLSI Self Aligned Local Interconnect Process

IP.com Disclosure Number: IPCOM000108374D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Ogura, S: AUTHOR [+2]

Abstract

Very large-scale integrated (VLSI) local interconnections must cross severe topography and ideally should make self-aligned contact to diffusions without causing damage to the diffused region. Such damage is often caused when the interconnecting material is dry etched over the contact area. The damage is usually observed as excessive removal of the contact caused by over etching due to poor selectivity between interconnect material and silicon. Alternative processes, such as that described in (*), use wet etching for selectivity and, therefore, avoid the over etch problem. Etch biases associated with this type of process, however, are no longer tolerable. It is also possible to inset an etch barrier, such as SiO2, between the interconnect material, e.g.

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VLSI Self Aligned Local Interconnect Process

       Very large-scale integrated (VLSI) local interconnections
must cross severe topography and ideally should make self-aligned
contact to diffusions without causing damage to the diffused region.
Such damage is often caused when the interconnecting material is dry
etched over the contact area.  The damage is usually observed as
excessive removal of the contact caused by over etching due to poor
selectivity between interconnect material and silicon. Alternative
processes, such as that described in (*), use wet etching for
selectivity and, therefore, avoid the over etch problem.  Etch biases
associated with this type of process, however, are no longer
tolerable.  It is also possible to inset an etch barrier, such as
SiO2, between the interconnect material, e.g., polysilicon, and the
diffusion but this has the effect of reducing the contact area and,
more importantly, requires the formation of additional conductive
layers to bridge the gap under the interconnect layer which has been
produced by the insulating etch barrier.

      In addition to good etch selectivity, a good local interconnect
material should be deposited by a CVD process to provide reliable
step coverage and should also be a material of low resistance
(typically 3-10 ohms/sq.).

      The procedure detailed in this article describes a local
interconnect process that utilizes CVD polysilicon to provide
excellent step coverage and incorporates controlled high pressure
oxidation as the method of selectively defining the interconnect
pattern.  Selectivity during oxidation is accomplished by masking the
poly with silicon nitride.  High conductivity is then achieved by
forming a self-aligned silicide, e.g., TiSi2, on the resulting
polysilicon lines.  A set of processing steps is shown below:

      Referring to Fig. 1, to produce the local inteconnect level a
layer of polysilicon (about 50-100 n...