Browse Prior Art Database

Cache Writing on Store Instruction Hits while the Cache is not Busy

IP.com Disclosure Number: IPCOM000108381D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Muhich, DD: AUTHOR [+3]

Abstract

RISC microprocessors which require two cache cycles for store instructions that hit can adversely affect system performance. Disclosed is a design to improve the system performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 92% of the total text.

Cache Writing on Store Instruction Hits while the Cache is not Busy

       RISC microprocessors which require two cache cycles for
store instructions that hit can adversely affect system performance.
Disclosed is a design to improve the system performance.

      Due to low cycle times seen in today's RISC microprocessors,
the store request cache hit scenario is very difficult to complete in
one cache cycle.  The time for determining if you have a cache hit is
close to a cycle. Following this with the cache write cycle to
complete the store request is difficult to accomplish in one cycle in
most designs.

      Breaking up the store request into two cache cycles is one way
of dealing with this problem.  The extra cache cycle, if followed
immediately after the first, may hold off other requests from being
cache arbed.  For combined instruction and data cache designs the
frequency of occurrence of this hold off may be high.

      Instead of following the cache hit check cycle with the write
cycle, thereby forcing a cache hold after every store request, the
disclosed design queues up the store request after determining cache
hit or miss and tries to perform the write cycle when there is a free
cycle (cache is not busy) in the cache.  A request is made to the
cache arbitor for doing the store write cycle.  If no one is
requesting the cache, then the arbitor accepts the request.

      If the memory queue becomes full and the write cycle has not
been p...