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Browse Prior Art Database

Wired-in Hash Function for Data Cache Address Calculation

IP.com Disclosure Number: IPCOM000108384D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR [+3]

Abstract

In today's high-performance RISC workstations, it takes at least two cycles to perform a simple load instruction; one cycle calculating effective address and at least one more cycle accessing the cache. This one-cycle delay creates a bubble in the pipeline and becomes a major performance issue in high-performance processors. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Wired-in Hash Function for Data Cache Address Calculation

       In today's high-performance RISC workstations, it takes
at least two cycles to perform a simple load instruction; one cycle
calculating effective address and at least one more cycle accessing
the cache.  This one-cycle delay creates a bubble in the pipeline and
becomes a major performance issue in high-performance processors.

                            (Image Omitted)

      This invention devises a scheme to eliminate this one-cycle
delay.  Instead of calculating the effective address by adding up
base address and offset, which accounts for a significant delay in a
high-speed machine, a simple hash function is used to generate the
cache access address. The hash function is implemented by wiring
certain bits of base address and offset directly to the data cache
address lines, which will not introduce any delay in the cache access
path; therefore, a load instruction can be executed in a single
cycle.

      In this system, both cache and directory are accessed by hashed
address, and high-order bits of effective address and segment ID are
stored in directory to identify each cache line.