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Browse Prior Art Database

Chip Yield Enhancement for Large Wafers

IP.com Disclosure Number: IPCOM000108405D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Joshi, ML: AUTHOR [+3]

Abstract

A method is described for mixing chips of different complexities on the same wafer to enhance chip yield. The method exploits the fact that, for many reasons, defect density on a wafer tends to be greater near the edge than near the center. Suppose there are two chip designs in the same technology which have different sizes and/or different groundrule requirements. The chip type that has the most stringent processing requirements would be placed in the central portion of the wafer. Chips with relaxed processing requirements for groundrules, performance and power requirements would be placed around the periphery of the wafer. The centrally located chips would have the best yield possible for the specified technology at the specified chip size and groundrules.

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Chip Yield Enhancement for Large Wafers

      A method is described for mixing chips of different
complexities on the same wafer to enhance chip yield.  The method
exploits the fact that, for many reasons, defect density on a wafer
tends to be greater near the edge than near the center.  Suppose
there are two chip designs in the same technology which have
different sizes and/or different groundrule requirements.  The chip
type that has the most stringent processing requirements would be
placed in the central portion of the wafer.  Chips with relaxed
processing requirements for groundrules, performance and power
requirements would be placed around the periphery of the wafer.  The
centrally located chips would have the best yield possible for the
specified technology at the specified chip size and groundrules.  The
peripherally located chips would be less sensitive to the inevitable
increase in defect density and parameter variation near the wafer
edge, and would have yields better than would be possible from
centrally located chip types placed near the periphery.

      Disclosed anonymously.