Browse Prior Art Database

Adjustable Wiring Porosity in Flexible Global Array Design

IP.com Disclosure Number: IPCOM000108406D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 28K

Publishing Venue

IBM

Related People

Iadanza, JA: AUTHOR [+3]

Abstract

Adding variable wire-through (porosity) capability to a standard circuit or array design program provides versatility to optimize use of first and second level wiring in a design. This capability allows minimization of space allowed for wiring in a wide range of array size and word dimensions.

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Adjustable Wiring Porosity in Flexible Global Array Design

      Adding variable wire-through (porosity) capability to a
standard circuit or array design program provides versatility to
optimize use of first and second level wiring in a design.  This
capability allows minimization of space allowed for wiring in a wide
range of array size and word dimensions.

      In conventional engineering design system (EDS) programs a
fixed wiring porosity, e.g., 50% has been used for first and second
level wiring through macro-circuit elements from which large-scale
circuit arrays are laid out (grown).  By adding key words to the EDS
program for porosity control for both first and second level wiring
to those describing number of words and bits per word, much more
efficient use of semiconductor area is achieved. Limits to array or
word dimensions caused previously by fixed porosity are also
eliminated.

      Disclosed anonymously.