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Reduced Reaction Between Si And SiO2 at a Si-SiO2 Interface

IP.com Disclosure Number: IPCOM000108430D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Raider, SI: AUTHOR

Abstract

Described is a fabrication technique for thin film devices through the addition of SiO into an SiO2 inert anneal ambient. The result is an inhibiting of the reaction between Si and SiO2, which degrades the oxide.

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Reduced Reaction Between Si And SiO2 at a Si-SiO2 Interface

      Described is a fabrication technique for thin film devices
through the addition of SiO into an SiO2 inert anneal ambient.  The
result is an inhibiting of the reaction between Si and SiO2, which
degrades the oxide.

      The reaction between Si and SiO2, after annealing in an inert
ambient, such as vacuum, Ar, He, etc., at elevated temperatures,
leads to degradation of electrical properties of metal oxide
semiconductor (MOS) structures.  If annealing is continued, holes are
formed in the oxide by the Si reaction with the SiO12.  The degraded
electrical properties arise from the initial stages of this reaction
consuming SiO12 prior to its visible detection as oxide holes.

      The interfacial reaction between Si and SiO2 is described by
the equation:  Si + SiO2 --> 2 SiO.  To shift the direction of this
reaction and to inhibit SiO formation at the interface, SiO is
introduced into the annealing ambient.  Preliminary studies indicate
that void formation is prevented during the anneal in an SiO
environment.  A high density of voids are detected in a control
sample. A relatively low density of line defects (stacking faults)
appear in the structure exposed to SiO.

      As a result, the addition of SiO to the anneal ambient is
useful in inhibiting the interfacial reaction between Si and SiO2 and
should be particularly effective during annealing poly-Si on SiO2
films.

      Disclosed ...