Browse Prior Art Database

Maximization of Self-Test Coverage in a Hardware Design

IP.com Disclosure Number: IPCOM000108441D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Jacob, F: AUTHOR

Abstract

Disclosed is a system allowing the maximization of the self-test coverage in a chip using the LSSD design, and the self-test structure commonly used within IBM. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

Maximization of Self-Test Coverage in a Hardware Design

       Disclosed is a system allowing the maximization of the
self-test coverage in a chip using the LSSD design, and the self-test
structure commonly used within IBM.

                            (Image Omitted)

      The self-test coverage is limited in today's designs by the
width of combinatory logic cones, i.e., a large "AND" cone will have
a very low probability of being tested, just because the 0 state is
easily generated using random patterns, while the 1 state is rarely
simulated.

      A way to solve this problem is to affect a weight to the random
patterns, so that each cone can receive the appropriate random
values.  A way of implementing the appropriate weighting of the
random values is described hereafter.

      The SRLs will be affected at the chip design to a given
channel, each channel having a weight given by the combinatory logic
connected to the PRPG.  Each SRL will then have the correct weight,
depending on the channel it belongs to.

      The SRL assignment to a given channel will be computed by
existing program, using the combinatory logic connected to the input
of the SRL.  Remember that both Clock logic and Data logic cones must
be combined to compute total SRL weight.

      The method allows fast test coverage to be attained (faster
than with unweighted random pattern), and allows test of circuitry
that would not otherwise be tested. ...