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Browse Prior Art Database

Integral Instruction Fetch Line Buffer in Cache

IP.com Disclosure Number: IPCOM000108452D
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Henry, G: AUTHOR [+3]

Abstract

Disclosed is a cache mechanism supporting both instruction fetch and data load/store in combination with store back buffers, reload buffers and fetch line buffers. The added feature disclosed is the integrated fetch line buffer contained within the cache macro of a VLSI Processor chip. By integrating the fetch line buffer within the cache macro a reduction in silicon space on the VLSI chip is realized. Also higher effective cache bandwidth is achieved.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Integral Instruction Fetch Line Buffer in Cache

       Disclosed is a cache mechanism supporting both
instruction fetch and data load/store in combination with store back
buffers, reload buffers and fetch line buffers.  The added feature
disclosed is the integrated fetch line buffer contained within the
cache macro of a VLSI Processor chip. By integrating the fetch line
buffer within the cache macro a reduction in silicon space on the
VLSI chip is realized. Also higher effective cache bandwidth is
achieved.

      In mixed I/D cache implementations wiring to and from the cache
macro presents quite a problem for a VLSI chip designer.  The cache
must supply data to the fix point data in unit for fixed point loads,
the floating point data in unit for floating point loads, the
instruction fetch unit for fetch data, and the memory unit for store
back data. The cache also receives data from the fixed point
execution units for fix point stores, the floating point execution
units for floating point stores, and the memory unit for reload data.
These inputs and outputs to/from the cache array are shown in the
figure.

      As shown in the figure, the Fetch Line Buffer and Shift Mux are
added to the cache macro with a 64-bit output to feed the Instruction
Queue.  This arrangement allows the cache to be accessed one cycle
per 256 bits accessed.  The 256 bits are latched into Fetch Line
Buffer.  The Shift Mux and 64-bit output supports the Instruction
Queue while othe...